1. Field of the Invention
The following invention relates to semiconductor device fabrication and more particularly to lithography techniques for reducing the real estate taken to form integrated circuits.
2. Related Art
Semiconductor device manufacturing is basically done by laying out a design, transferring the design to a photolithography mask, and printing the design pattern onto a semiconductor substrate or wafer.
Semiconductor chips are manufactured using a series of masks in the lithographic process. During lithography, successive patterns of materials on and regions in a semiconductor wafer are chemically or photochemically induced onto the surface of the wafer using the mask as a template. The patterns, including lines and holes, define the circuit elements, such as transistors.
Initially, the semiconductor wafer is covered with resist material, such as photoresist. The resist material is responsive to incident energy, such as an electromagnetic radiation. Examples of electromagnetic waves used are visible light, ultraviolet light, electron beams, and x-rays. Where the resist material is exposed to the radiation, it chemically activates the resist, by for example etching a hole in the substrate.
In lithography, the mask is used to determine where the electromagnetic radiation is permitted to contact the resist material. The mask functions to mask certain regions of the resist material from the incident energy but not other regions, by permitting the radiation to pass through some regions (called transmissive regions), and preventing the radiation from passing through other regions (called non-transmissive regions).
There are different types of lithography. One type of lithography uses projection optics. In a typical state of the art tool of this type of lithography, the pattern on the mask is reduced in size using special optical lenses before being transmitted to the resist material using the incident energy. This permits the mask to be produced more easily and cost-effectively. For example, the mask pattern can be reduced four times from its original size to create the actual pattern on the substrate. In this manner, the pattern on the mask is used to create pattern lines or grooves on the substrate.
The pattern lines are used to create semiconductor devices, such as transistors. For a typical DRAM chip, enormous arrays of memory cells are created from the transistors, which in turn are comprised of the drawn pattern lines. The memory cells are very regular structures, of infinitesimal size. For modern chips, pattern lines having dimensions on the order of less than 200 nanometers need to be drawn, to keep the size of the chip small.
As noted, in one type of lithography, optical equipment is used to transfer the mask pattern onto the resist material. As a result of the optical interference which occur during pattern transfer, images formed on the device substrate deviate from their ideal dimensions and shape as represented on the mask. With current technologies, the dimensions of the pattern lines are on the order of, or even smaller than, the wavelengths of the incident energy (e.g., photo source) exposed to the resist (e.g., photoresist) material.
These deviations depend on the characteristics of the patterns as well as a variety of process conditions. These deviations are usually referred to by the term optical proximity effect. Their degree of severity depend on the resolution capability of an optical lithography system. The resolution is defined by the equation k1xcex/NA, where k1 is a constant, xcex is the illumination wavelength, and NA is the numerical aperture of the imaging system.
Optical lithography for a k1 factor below 0.5 complicates proximity curves immensely, which means the mentioned deviations of the printed patterns from the original mask pattern increase further. For example, a problem arises in that if the process is optimized for the array of DRAM devices (e.g., equal lines and spaces), then more isolated lines outside the array could be printed smaller or larger depending on the line width and the environment, or surrounding composition of the shape placements. These effects may even result in disappearing lines or spaces. These deviations have the disadvantage of significantly reducing chip performance, possibly even causing the chip to fail.
Alternatively to the costly development of processes with ever higher effective resolution is the selective biasing of mask patterns to compensate for the pattern distortion occurring during wafer processing. The term xe2x80x9coptical proximity correctionxe2x80x9d (OPC) is used to describe the process of selective mask biasing, even though the trend exists to include pattern distortions unrelated to the optical image transfer.
Many approaches have been pursued to compensate for the results of the optical interference occurring during pattern transfer, namely that the images formed on the device substrate deviate from their ideal images. Usually the process is optimized for one feature type such as the DRAM array and as a result other features, such as isolated lines or spaces, are degraded in their lithographic capability.
To defeat these negative effects, developers have used a variety of techniques. One technique is to increase the NA, to effect the resolution defined by k1xcex/NA. Another technique is to modify the coherence of the incident energy (e.g., incident light source). Another technique is to reduce the wavelength of the illumination. Another technique is to phase shift the mask. The invention disclosed here can be used on a binary or phase shifted mask.
One technique is to modify the dimensions of the mask, such that the mask images used generate the edge pattern lines at different dimensions from the non-edge pattern lines. This is a type of OPC solution. A computer processor is used to generate the amount of the mask image distortions, such that when the patterns are transferred onto the substrate and the inevitable optical proximity effects take place, the edge pattern lines are of the same dimensions as the non-edge pattern lines. Unfortunately, it is a difficult, time-consuming, and often non-effective enterprise to account for the proximity effects by distorting the mask patterns. Additionally, there are cases for which there is no such exact OPC solution.
Another technique has been to add so-called xe2x80x9cdummyxe2x80x9d lines at the end of the arrays. Additional pattern lines, other than the number of pattern lines desired, are added at the edges of the arrays. It is these dummy lines that are distorted during photolithography, and the first non-dummy line is now in an array-like environment.
Unfortunately, the dummy lines are wasteful of space on the chip. The smaller the k1 constant gets, the more additional dummy lines that must be added.
What is required is a way of preventing or minimizing these deleterious effects without sacrificing cost and real estate on the chip, or providing an enormous amount of additional processing.
The present invention is directed to a method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask.
The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions.
The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions.
The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions.
The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.
The method further includes creating a design layout for the semiconductor circuit wafer; and producing the mask from the design layout. The producing step can be performed using optical photolithography. This includes radiating an energy source through the pattern regions, the energy source having a wavelength in the range of the widths of the pattern lines formed from the non-edge pattern regions and the widths of the pattern lines formed from the edge pattern regions. It can also include reducing the pattern regions in size by a fixed multiple to produce the pattern lines formed from the non-edge pattern regions and the pattern lines formed from the edge pattern regions.
The method includes using an OPC tool to calculate the widths of the edge pattern regions. The dimensions of the pattern lines can be widths of the pattern lines.
The above-noted any two pattern regions can include one of the non-edge pattern regions and one of the edge pattern regions. Also, these any two pattern regions can include a first of the edge pattern regions and a second of the edge pattern regions. Finally, the any two pattern regions can include a first of the pattern regions and a second of the pattern regions positioned adjacent to one another.